1、关联Quartus II 和Modelsim 软件

打开Quartus II 软件

关联modlesim软件

配置工程仿真软件

现在Quartus II 和Modelsim 软件已经关联在一起了。

2、生成vt文件（Verilog test bench）

3、编写vt文件

生成后的vt文件：

修改后

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "02/10/2022 09:24:50"
                                                                                
// Verilog Test Bench template for design : emg_fpga_top
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ns
module emg_fpga_top_vlg_tst();
// constants                                           
// general purpose registers
//reg eachvec;    没用的信号
// test vector input registers
reg Ads_irq_8;
reg SPI_miso;
reg Start_data_flag;
reg sys_clk;
reg sys_rst_n;
// wires                                               
wire SPI_cs_n;
wire SPI_mosi;
wire SPI_sck;
wire led_b;
wire led_g;
wire led_r;
wire uart_txd;

// assign statements (if any)                          
emg_fpga_top i1 (
// port map - connection between master ports and signals/registers   
	.Ads_irq_8(Ads_irq_8),
	.SPI_cs_n(SPI_cs_n),
	.SPI_miso(SPI_miso),
	.SPI_mosi(SPI_mosi),
	.SPI_sck(SPI_sck),
	.Start_data_flag(Start_data_flag),
	.led_b(led_b),
	.led_g(led_g),
	.led_r(led_r),
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.uart_txd(uart_txd)
);
initial begin           //付初值                                              
    sys_clk=1'b0;       //系统时钟付初值
    sys_rst_n=1'b0;     //复位信号付初值
    #100 sys_rst_n=1'b1;//延时100ns，把复位信号拉高
    
    #1000 $stop; //程序仿真时运行1000ns，停止仿真
end       
 
//产生时钟翻转信号 
always     #10 sys_clk=~sys_clk;//系统时钟是50mhz，周期是20ns，那么就是没10ns，时钟翻转一次                                            
                                                  
endmodule