EDA课程设计

module vend(onei,halfi,collectLED,half_out,dispense,reset,clk);
parameter idle=0,half=1,one=2,oneAhalf=3,two=4,twoAhalf=5,three=6;
(*chip_pin="M21"*)input onei;
(*chip_pin="N21"*)input halfi;
(*chip_pin="AB28"*)input reset;
(*chip_pin="AC28"*)input variety;
(*chip_pin="Y2"*)input clk;
(*chip_pin="AA17,AB16,AA16,AB17,AB15,AA15,AC17,AD18,AC18,AB18,AH19,AG19,AF18,AH18"*)output reg[13:0] collectLED;
(*chip_pin="G15"*)output half_out;
(*chip_pin="H15"*)output dispense;
reg collect,half_out,dispense;
reg[2:0] D;
reg[2:0] N;

always@(posedge clk) begin 
	if(!reset)
		D<=idle;
	else
		D<=N;
end

always@(*) begin
	//begin dispense=0;collect=0;half_out=0;D=idle;end
	case(variety)
		0:case(D)
			idle:if(halfi==1) N=half;
				else if(onei==1) N=one;
			half:if(halfi==1) N=one;
				else if(onei==1) N=oneAhalf;
			one:if(halfi) N=oneAhalf;
				else if(onei==1) N=two;
			oneAhalf:if(halfi==1) N=two;
				else if(onei==1)
					N=idle;
			two:if(halfi==1) N=idle;
				else if(onei==1) N=idle;
			default:N=idle;
		endcase
		1:case(D)
			idle:if(halfi==1) N=half;
				else if(onei==1) N=one;
			half:if(halfi==1) N=one;
				else if(onei==1) N=oneAhalf;
			one:if(halfi) N=oneAhalf;
				else if(onei==1) N=two;
			oneAhalf:if(halfi==1) N=two;
				else if(onei==1) N=twoAhalf;
			two:if(halfi==1) N=twoAhalf;
				else if(onei==1) N=idle;
			twoAhalf:if(halfi==1) N=idle;
				else if(onei==1) N=idle;
			default:N=idle;
		endcase
	endcase
end

always@(posedge clk) 
begin
	case(variety)
	0:if(!reset)
			dispense<=1;
		else
		case(D)
			idle:dispense<=0;
			half:dispense<=0;
			one:dispense<=0;
			oneAhalf:if(halfi==1) dispense<=1;
				else dispense<=0;
			two:if(halfi==1||onei==1) dispense<=1;
				else dispense<=0;
			default:dispense<=0;
		endcase
	1:if(!reset)
			dispense<=1;
		else
		case(D)
			idle:dispense<=0;
			half:dispense<=0;
			one:dispense<=0;
			oneAhalf:dispense<=0;
			two:if(onei==1) dispense<=1;
				else dispense<=0;
			twoAhalf:if(halfi==1||onei==1) dispense<=1;
				else dispense<=0;
			default:dispense<=0;
		endcase
end

always@(posedge clk) 
begin
	case(variety)
		0:if(!reset)
				half_out<=0;
			else
			if(D==two&&onei==1) half_out=1;
			else half_out=0;
		1:if(!reset)
				half_out<=0;
			else
			if(D==twoAhalf&&onei==1) half_out=1;
			else half_out=0;
end

always@(D)
begin
	case(D)
		idle:collectLED=14'b0000001_0000001;	
		half:collectLED=14'b0000001_0100100;
		one:collectLED=14'b1001111_0000001;
		oneAhalf:collectLED=14'b1001111_0100100;
		two:collectLED=14'b0010010_0000001;
		twoAhalf:collectLED=14'b0010010_0100100;
		default:collectLED=0000001_0000001;
	endcase
end

endmodule