AXI 总线

module axi_lite_controller#(parameter ADDR_WIDTH = 5)
(
// clock and reset
aclk,
aresetn,
// write address channel
awaddr,
awvalid,
awready,

    // read address channel
    araddr,
    arready,
    arvalid,
    
    // write data channel
    wvalid,
    wready,
    wdata,
    
    // read data channel
    rvalid,
    rready,
    rdata,
    
    // write response channel
    bvalid,
    bready
);