4K边界可以看成是master侧对边界的主动保护。比如两个IP地址是连序的，那么在第一个IP末尾附近地址发起一个长burst跨越边界，第二个设备实际上没有完成前面的AW或者AR通道的握手，这个会引起总线异常。
如果是大片地址的slave设备，并且本身没有4K边界的要求，双方约定好，master侧可以不进行4K边界检测。
it’s a compromise between the number of address bits that need decoding and the minimum space that needs to be allocated to each slave.
As examples, you could say a protocol requires a minimum of 1MB per slave, so a lot of wasted address space in most slave designs, but the decoder only has to decode 12 address bits (simpler combinatorial logic), or an opposite extreme, a minimum of 4 bytes per slave, so no wasted address space in each slave, but the decoder then has to decode 30 address bits (not great for combinatorial timing).
So 4KB for AXI is a compromise, not too much “wasted” address space in small slaves, and not too many address lines to decode.
1KB or 4KB isn’t going to be an issue for the number of slaves possible on the bus (4M or 1M), so it is just address bits for decoding against possible wasted space in each minimum slave footprint that is the compromise decision.
1KB was what was specified for AHB (I don’t think APB specifies any minimum, instead it just takes the minimum defined by whatever bus is driving the APB bridge), and the reason why this was increased to 4KB in AXI would be that AXI is a newer protocol than AHB, and data bus widths in common use have grown wider between when AHB and AXI were defined, so if looking at maximum bursts of 16 transfers, 4KB allows more flexibility for typical width maximum length bursts within one slave region, before the master has to look at ending one burst and starting a new one.
https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/1416/4-kbyte-boundary-space