Veriloga实现十进制转二进制8bit数

//  veriloga_dec2bin8, veriloga

`include "constants.vams"
`include "disciplines.vams"

module veriloga_dec2bin8(vin,vout,vdd,vss);

//vdd is the output voltage high level
//parameter real vdd=5.0;
//parameter real trise = 0 from [0:inf);
//parameter real tfall = 0 from [0:inf);
//parameter real tdel = 0 from [0:inf);

input vin;
output [0:7] vout;
voltage vin;
voltage [0:7] vout;

inout vdd,vss;

voltage vdd,vss;
real sample;
integer result[0:7];
integer i;
genvar j;

analog begin
sample=V(vin);
for(i=7;i>=0;i=i-1) begin
    if(sample>=(1<<i)) begin
        result[i]=1;
        sample=sample-(1<<i);
    end
    else begin
        result[i]=0;
    end
end

//there is Z<+A?X:Y mathod，but I don't know where there is error.

for(j=0;j<=7;j=j+1) begin
    if(result[j]==1) begin
        V(vout[j])<+V(vdd);
    end
    else if(result[j]==0) begin
        V(vout[j])<+V(vss);
    end
end
end
endmodule

//程序说明：输入是一个十进制表示的vin，可以用vdc直流源给，直流大小就是vin，输出是8bit的信号，信号高电平是vdd，低电平是vss。可以改成64bit内的任意位数输出，超过64bit我测试过有问题，可能是数据类型的错误。