使用Modelsim直接仿真应该注意以下几个问题：
（1）分别建立rtl、sim和tb三个文件夹，在rtl中放入顶层.v文件，在sim中放入glbl.v和sim_tb_top.do文件，
其中glbl.v中内容为：
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
sim_tb_top.do内容为：
vlib work
vlog ../tb/*.v
vlog ../sim/glbl.v
vlog ../rtl/*.v
vsim -t ps -novopt +notimingchecks -L xilinxcorelib_ver -L unisims_ver work.sim_tb_top glbl -do wave.do
#vsim -t ps -novopt +notimingchecks -L xilinxcorelib_ver -L unisims_ver work.sim_tb_top glbl
tb文件夹中放入sim_tb_top testbench文件。
（2）Modelsim操作
cd D:/modeltech_10.1c/zp_test_2/zp_test/sim（注意：斜杠为/）
do sim_tb_top.do
运行之后弹出Modelsim仿真框，加入想要查看的信号即可进行仿真。