用VHDL语言实现一个时延模块，可以满足任意时钟周期的时延。代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 

entity Delay is
generic(
	num     : integer    --设置要延迟的周期数
	);
port( 
	clk     : in std_logic;
	sig     : in std_logic;   
	del_sig : out std_logic
	);
end Delay;
architecture Delay of Delay is

signal sig_delay    : std_logic_vector(num-1 downto 0) := (others =>'0');

begin
	process(clk)
	begin
		if (clk'event and clk = '1') then
			sig_delay(0) <= sig;
			sig_delay(num-1 downto 1) <= sig_delay(num-2 downto 0);
		end if;	
	end process;
	del_sig <= sig_delay(num-1);
	
end Delay;