gradle task 传递参数_SystemVerilog教程之Task和Functions

SystemVerilog在Verilog 2001的Task和Function的基础上增加了在static Task和Function中声明automatic 变量的能力，以及在automatic Task和Function中声明static变量的能力。 

Tasks&Functions

Default Port Direction：除非声明为其他类型，否则任何端口都被视为input

Default Data TYpe：除非声明为其他类型，否则端口的数据类型是logic 类型。

begin..end：当使用多个语句时，没有必要使用begin..end

Variables ：Systemverilog允许使用本地static或dynamic 变量。

life time：SystemVerilog中的Task和Function可以是static或dynamic的。

wire：Wire数据类型不能在端口列表中使用;

Tasks

module task_intro ();initial begin  #1 doInit(4,5);  #1 doInit(9,6);  #1 $finish;endtask doInit (input bit [3:0] count, delay);  automatic reg [7:0] a;  if (count > 5) begin    $display ("@%g Returning from task", $time);    return;  end  #(delay) $display ("@%g Value passed is %d", $time, count);endtaskendmodule

输出

@6 Value passed is  4@7 Returning from task

Functions

module task_intro ();bit a ;initial begin  #1 a = doInit(4,5);  #1 a = doInit(9,6);  #1 $finish;endfunction bit unsigned doInit (bit [3:0] count, add);  automatic reg [7:0] b;  if (count > 5) begin    $display ("@%g Returning from function", $time);    return 0;  end  b = add;  $display ("@%g Value passed is %d", $time, count + b);  doInit = 1;endfunctionendmodule

输出

@1 Value passed is   9@2 Returning from function

Argument Passing

SystemVerilog提供了通过value 和reference将参数传递给Task 和function 的方法。 

Pass by value

在Verilog 1995/2001中，可以通过值将一个参数传递给Task 和function 。此时仿真工具会对参数值进行复制。

module function_by_value ();reg [7:0] data      ;reg       parity_out;integer   i         ;function parity; input [31:0] data; integer i; begin  parity = 0;  for (i= 0; i < 32; i = i + 1) begin    parity = parity ^ data[i];  end endendfunctioninitial begin      parity_out = 0;  data = 0;  for (i=250; i<256; i = i + 1) begin   #5 data = i;   parity_out = parity (data);   $display ("Data = %b, Parity = %b", data, parity_out);  end  #10 $finish;endendmodule

输出

 Data = 11111010, Parity = 0 Data = 11111011, Parity = 1 Data = 11111100, Parity = 0 Data = 11111101, Parity = 1 Data = 11111110, Parity = 1 Data = 11111111, Parity = 0

Pass by reference

Systemverilog可以通过reference传递参数，此时仿真器不会复制参数，而是将原始参数的reference传递给Task 和function。 
当参数通过reference传递时，调用者所做的任何更改都会影响原来的参数值。
当参数声明为const ref时，调用者就不能改变参数值。

module function_by_ref ();reg [7:0] data      ;reg       parity_out;time      ltime;function reg parity (ref reg [7:0] idata, const ref time tdata); parity = 0; for (int i= 0; i < 8; i ++) begin    parity = parity ^ idata[i]; end // We can modify the data passed through reference idata ++ ; // Something that is passed as const  ref, can  not be modified // tdata ++ ; This is wrongendfunctioninitial begin      parity_out = 0;  data = 0;  for (int i=250; i<256; i ++) begin   #5 data = i;   ltime = $time;   parity_out = parity (data, ltime);   $display ("Data = %00000000b, Parity = %b, Modified data : %b",      i, parity_out, data);  end  #10 $finish;endendmodule

输出

Data = 11111010, Parity = 0, Modified data : 11111011 Data = 11111011, Parity = 1, Modified data : 11111100 Data = 11111100, Parity = 0, Modified data : 11111101 Data = 11111101, Parity = 1, Modified data : 11111110 Data = 11111110, Parity = 1, Modified data : 11111111 Data = 11111111, Parity = 0, Modified data : 00000000

往期精彩

SystemVerilog教程之Verilog Basics  Part-I

SystemVerilog教程之Verilog Basics Part-II

SystemVerilog教程之Verilog Basics-III

SystemVerilog教程之Data Types Part-I

SystemVerilog教程之Data Types Part-II

SystemVerilog教程之Data Types Part-III

SystemVerilog教程之Data Types Part-4

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