multply.v
module multiply( // 乘法器
input clk, // 时钟
input mult_begin, // 乘法开始信号
input [63:0] mult_op1, // 乘法源操作数1
input [31:0] mult_op2, // 乘法源操作数2
output [63:0] product, // 乘积
output mult_end // 乘法结束信号
);
wire op1_sign; //操作数1的符号位
wire op2_sign; //操作数2的符号位
wire [31:0] op1_absolute; //操作数1的绝对值
wire [31:0] op2_absolute; //操作数2的绝对值
assign op1_sign = mult_op1[31];
assign op2_sign = mult_op2[31];
assign op1_absolute = op1_sign ? (~mult_op1+1) : mult_op1;
assign op2_absolute = op2_sign ? (~mult_op2+1) : mult_op2;
reg flag;
//第一个上升沿后begin=1&end=0flag=1表示可以开始运算，第二个上升沿之后乘数才开始左移
always@(posedge clk)
begin
if(mult_begin&!mult_end)
begin
flag<=1'b1;
end
else
begin
flag<=1'b0;
end
end
reg [63:0]process_op1;//被乘数
reg [31:0]process_op2;//乘数
assign mult_end=flag&~(|process_op2);
always@(posedge clk)
begin
if(flag)
begin
process_op1<=process_op1<<1;
process_op2<=process_op2>>1;
end
else if(mult_begin&!mult_end)
begin
process_op1<={32'b0,op1_absolute};
process_op2<=op2_absolute;
end
end
reg [63:0]part;
wire [63:0] partial_product;
assign partial_product = process_op2[0] ? process_op1:64'd0; //若此时y的最低位为1，则把x赋值给部分积partial_product，否则把0赋值给partial_product
always@(posedge clk)
begin
if(flag)
begin
part<=part+partial_product;
end
else if(mult_begin&!mult_end)
begin
part<=64'b0;
end
end
wire product_sign;
assign product_sign=op1_sign^op2_sign;
assign product = product_sign ? (~part+1) : part;
endmodule
display
//*************************************************************************
// > 文件名: multiply_display.v
// > 描述 ：乘法器显示模块，调用FPGA板上的IO接口和触摸屏
// > 作者 : LOONGSON
// > 日期 : 2016-04-14
//*************************************************************************
module multiply_display(
//时钟与复位信号
input clk,
input resetn, //后缀"n"代表低电平有效
//拨码开关，用于选择输入数
input input_sel, //0:输入为乘数1;1:输入为乘数2
input sw_begin,
//乘法结束信号
output led_end,
//触摸屏相关接口，不需要更改
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{调用乘法器模块}begin
wire mult_begin;
reg [31:0] mult_op1;
reg [31:0] mult_op2;
wire [63:0] product;
wire mult_end;
assign mult_begin = sw_begin;
assign led_end = mult_end;
multiply multiply_module (
.clk (clk ),
.mult_begin(mult_begin),
.mult_op1 (mult_op1 ),
.mult_op2 (mult_op2 ),
.product (product ),
.mult_end (mult_end )
);
reg [63:0] product_r;
always @(posedge clk)
begin
if (!resetn)
begin
product_r <= 64'd0;
end
else if (mult_end)
begin
product_r <= product;
end
end
//-----{调用乘法器模块}end
//---------------------{调用触摸屏模块}begin--------------------//
//-----{实例化触摸屏}begin
//此小节不需要更改
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//调用触摸屏的接口
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd触摸屏相关接口，不需要更改
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{实例化触摸屏}end
//-----{从触摸屏获取输入}begin
//根据实际需要输入的数修改此小节，
//建议对每一个数的输入，编写单独一个always块
//当input_sel为0时，表示输入数为乘数1
always @(posedge clk)
begin
if (!resetn)
begin
mult_op1 <= 32'd0;
end
else if (input_valid && !input_sel)
begin
mult_op1 <= input_value;
end
end
//当input_sel为1时，表示输入数为乘数2
always @(posedge clk)
begin
if (!resetn)
begin
mult_op2 <= 32'd0;
end
else if (input_valid && input_sel)
begin
mult_op2 <= input_value;
end
end
//-----{从触摸屏获取输入}end
//-----{输出到触摸屏显示}begin
//根据需要显示的数修改此小节，
//触摸屏上共有44块显示区域，可显示44组32位数据
//44块显示区域从1开始编号，编号为1~44，
always @(posedge clk)
begin
case(display_number)
6'd1 :
begin
display_valid <= 1'b1;
display_name <= "M_OP1";
display_value <= mult_op1;
end
6'd2 :
begin
display_valid <= 1'b1;
display_name <= "M_OP2";
display_value <= mult_op2;
end
6'd3 :
begin
display_valid <= 1'b1;
display_name <= "PRO_H";
display_value <= product_r[63:32];
end
6'd4 :
begin
display_valid <= 1'b1;
display_name <= "PRO_L";
display_value <= product_r[31: 0];
end
default :
begin
display_valid <= 1'b0;
display_name <= 48'd0;
display_value <= 32'd0;
end
endcase
end
//-----{输出到触摸屏显示}end
//----------------------{调用触摸屏模块}end---------------------//
endmodule
tb
`timescale 1ns / 1ps
// Company:
// Engineer:
//
// Create Date: 17:13:38 04/15/2016
// Design Name: multiply
// Module Name: F:/new_lab/multiply/tb.v
// Project Name: multiply
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: multiply
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module tb;
// Inputs
reg clk;
reg mult_begin;
reg [31:0] mult_op1;
reg [31:0] mult_op2;
// Outputs
wire [63:0] product;
wire mult_end;
// Instantiate the Unit Under Test (UUT)
multiply uut (
.clk(clk),
.mult_begin(mult_begin),
.mult_op1(mult_op1),
.mult_op2(mult_op2),
.product(product),
.mult_end(mult_end)
);
initial begin
// Initialize Inputs
clk = 0;
mult_begin = 0;
mult_op1 = 0;
mult_op2 = 0;
// Wait 100 ns for global reset to finish
#100;
mult_begin = 1;
mult_op1 = 32'H00001111;
mult_op2 = 32'H00001111;
#400;
mult_begin = 0;
#500;
mult_begin = 1;
mult_op1 = 32'H00001111;
mult_op2 = 32'H00002222;
#400;
mult_begin = 0;
#500;
mult_begin = 1;
mult_op1 = 32'H00000002;
mult_op2 = 32'HFFFFFFFF;
#400;
mult_begin = 0;
#500;
mult_begin = 1;
mult_op1 = 32'H00000002;
mult_op2 = 32'H80000000;
#400;
mult_begin = 0;
// Add stimulus here
end
always #5 clk = ~clk;
endmodule
xdc
set_property PACKAGE_PIN AC19 [get_ports clk]
set_property PACKAGE_PIN H7 [get_ports led_end]
set_property PACKAGE_PIN Y3 [get_ports resetn]
set_property PACKAGE_PIN AC21 [get_ports input_sel]
set_property PACKAGE_PIN AD24 [get_ports sw_begin]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports led_end]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports input_sel]
set_property IOSTANDARD LVCMOS33 [get_ports sw_begin]
#lcd
set_property PACKAGE_PIN J25 [get_ports lcd_rst]
set_property PACKAGE_PIN H18 [get_ports lcd_cs]
set_property PACKAGE_PIN K16 [get_ports lcd_rs]
set_property PACKAGE_PIN L8 [get_ports lcd_wr]
set_property PACKAGE_PIN K8 [get_ports lcd_rd]
set_property PACKAGE_PIN J15 [get_ports lcd_bl_ctr]
set_property PACKAGE_PIN H9 [get_ports {lcd_data_io[0]}]
set_property PACKAGE_PIN K17 [get_ports {lcd_data_io[1]}]
set_property PACKAGE_PIN J20 [get_ports {lcd_data_io[2]}]
set_property PACKAGE_PIN M17 [get_ports {lcd_data_io[3]}]
set_property PACKAGE_PIN L17 [get_ports {lcd_data_io[4]}]
set_property PACKAGE_PIN L18 [get_ports {lcd_data_io[5]}]
set_property PACKAGE_PIN L15 [get_ports {lcd_data_io[6]}]
set_property PACKAGE_PIN M15 [get_ports {lcd_data_io[7]}]
set_property PACKAGE_PIN M16 [get_ports {lcd_data_io[8]}]
set_property PACKAGE_PIN L14 [get_ports {lcd_data_io[9]}]
set_property PACKAGE_PIN M14 [get_ports {lcd_data_io[10]}]
set_property PACKAGE_PIN F22 [get_ports {lcd_data_io[11]}]
set_property PACKAGE_PIN G22 [get_ports {lcd_data_io[12]}]
set_property PACKAGE_PIN G21 [get_ports {lcd_data_io[13]}]
set_property PACKAGE_PIN H24 [get_ports {lcd_data_io[14]}]
set_property PACKAGE_PIN J16 [get_ports {lcd_data_io[15]}]
set_property PACKAGE_PIN L19 [get_ports ct_int]
set_property PACKAGE_PIN J24 [get_ports ct_sda]
set_property PACKAGE_PIN H21 [get_ports ct_scl]
set_property PACKAGE_PIN G24 [get_ports ct_rstn]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_rst]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_cs]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_rs]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_wr]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_rd]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_bl_ctr]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports ct_int]
set_property IOSTANDARD LVCMOS33 [get_ports ct_sda]
set_property IOSTANDARD LVCMOS33 [get_ports ct_scl]
set_property IOSTANDARD LVCMOS33 [get_ports ct_rstn]
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