Lattice DCS (Dynamic Clock Select)
1、Why do I get a netsanitycheck PAR error when a MUX drives the clock of a IDDR/ODDR component?
The netsanitycheck error indicates general routing is used to drive the IDDR and/or ODDR components. The logic must be modified to use dedicated clock resources:Solution 1: Do not use generic logic (e.g. MUX implemented by LUTs) to generate the clock for the IDDR/ODDR. The solution is to use a DCS for the MUX function instead. Solution 2: Use the dedicated clock routing resources when using a DCS. A typical application is to use the DCS to switch between a PLL input and PLL output clock. But beware, if a dedicated PLL input pin and the PLL CLKOS output are the two inputs of a DCS, the PLL input pin will go to the DCS via the general routing net. There are two possible work-arounds: A) Route the PLL input to the PLL’s CLKOK while bypassing the PLL. Then the CLKOS and the CLKOK PLL outputs can be connected to the DCS with the dedicated routing resource. b) Route the PLL input from a primary clock pin, not a PLL input pin. The PLL input and the CLKOS can be fed to the DCS directly without any problem.
2、How to locate DCS in preference file for FPGA?
DCS is a Digital clock select, a clock multiplexer, which is available in devices such as LatticeSC/M, LatticeXP2, LatticeECP2/M and LatticeECP3.
How to assign DCS locations in .lpf preference file?The syntax is shown in the following example: LOCATE COMP “xxxx” SITE “DCSTB” ; The “xxxx” is the instantiation name in your VHDL or Verilog code.
The DCS locations in LatticeSC family are at four edges – two per edge.DCSTA, DCSTBDCSLA, DCSLBDCSRA, DCSRBDCSBA, DCSBBwhere the letter right after “DCS” shows the edge the DCS is located: T is top, L is left, R is right, B is bottom.
The DCS locations in LatticeXP2, LatticeECP2/M and LatticeECP3 families are near the Center Switch Box – two per quadrant.ULDCS1, ULDCS0URDCS1, URDCS0LLDCS1, LLDCS0LRDCS1, LRDCS0where UL is upper-left, UR is upper-right, LL is lower-left, LR is lower-right. These examples (in VHDL or Verilog) can be found in apps note for those devices that has DCS available. Here is one for XP2, ECP2/M and ECP3 in Verilog:
DCS dcs_inst (.CLK1(DCS_clkin1), .CLK0(DCS_clkin0), .SEL(DCS_sel), .DCSOUT(DCS_clkout));
In the preference file, you can assign its location like this:
LOCATE COMP “dcs_inst” SITE “LLDCS0” ;
3、How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE Report?
A DCS (Dynamic Clock Select) element only drives primary clock nets.That is why the DCS cell delay is not presented by itself in a Place and Route TRACE Report.A TRACE report will show a 0 delay through the DCS cell.Instead, the sum of the DCS and and primary clock network delay is lumped as a whole into the DCS output clock net delay in the TRACE report.Below is an example from a TRACE report, where the DCS cell delay (MUX_DEL) is 0 and the total cell and route delay is lumped into the global clock (ROUTE):Name Fanout Delay (ns) Site ResourcePADI_DEL — 0.457 C12.PAD to C12.PADDI clk0ROUTE 1 0.870 C12.PADDI to ULDCS0.CLK0 clk0_cMUX_DEL — 0.000 ULDCS0.CLK0 to ULDCS0.DCSOUT DCSInst0ROUTE 4 0.474 ULDCS0.DCSOUT to IOL_T2A.CLK dcsout_inferred_clock——–1.801 (25.4% logic, 74.6% route), 2 logic levels.
4、How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. When selection input is toggled, the DCS looks for the current clock waveform as well as the new clock waveform. When one clock input is not operating, the simulation will not work because there is no current clock wave for information. The hardware will switch from in-operative clock to working clock eventually but may suffer additional delay for DCS output to settle down to active clock. If user must switch between inactive clock and active clock, regular mux must be used. Refer to Lattice Technical note, TN1178: LatticeECP3 sysCLOCK/PLL Design and Usage Guide. It is available at the link below.
http://www.latticesemi.com/documents/tn1178.pdf
5、What do users need to consider when using the LatticeECP2/M Dynamic Clock Select (DCS)?
Documentation on LatticeECP2/M’s DCS is located in page 10-29 of the LatticeECP2/M Family Handbook. The link to the Handbook can be located here.One of the issues that users will run into when using the DCS is having too many clocks to the DCS. This results in an unroutable design. The description below explains the relationship between the number of clocks into the DCS and the number of DCS used.In a LatticeECP2/M device a DCS can have its input come from either general purpose routing, another clock (via general purpose routing), or clock input I/O. There are a total of 8 available general purpose routing inputs to the 8 DCS in a LatticeECP2/M. As a result, there are only 8 unique sources that can go to the 8 DCS. However, each DCS can receive any two combination of the 8 inputs.Another issue that users might encounter is unsuccessful switching between the two clock inputs into a DCS. Unsuccessful switching usually occurs when one of the input clocks is not running (i.e. stuck at logic HIGH or at logic LOW). For proper switching between the two clock inputs, both clock inputs must be running. This requirement is present because the DCS circuits uses the clock edges to do the proper switching. So, users will need to consider whether DCS is the proper clock multiplexer solution when at least one of the clock inputs is not a free running clock. An alternative solution for a non-free running clock is LUT-based clock multiplexer.Users can also cascade DCS. However, this creates a long delay between the inputs of the first and last DCS’ in the cascade. Users will need to take this into consideration (i.e. whether the long delay is acceptable). Note that to cascade DCS, some parts of the cascade connection use general purpose routing.
6、Will the command sequence implemented in the DCS ROM of the DSI TX reference design work for all displays?
The command sequence implemented in the DCS ROM of the Reference Design were taken from the source code of Android based working setup. The command sequence only works for the Wintek display described in the user guide. It is the responsibility of the designer to change the initialization values of the DCS ROM to the required command sequence for the display used in the design.For the appropriate command sequence please contact the display manufacturer.
7、How can I select between 2 clocks and avoid gating it using fabric resources?
The ECP family of devices all have a Digital Clock Select (DCS) component. These components allow the user to do clock selection without leaving primary clock routing. For more information on the DCS in each architecture, please reference the sysCLOCK technical note for that family.
8、How can I determine what clock resources are being used?
To determine what clock resources are being used refer to the Clock Report which is found in the ispLEVER .PAR Report. Below is an example: —————— Clock Report —————— Global Clock Resources: CLK_PIN : 1 out of 6 (16%) PLL : 0 out of 10 (0%) DCS : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY “clk_c” from comp “clk” on CLK_PIN site “C12 (PT76A)”, clk load = 12 PRIMARY : 1 out of 8 (12%) DCS : 0 out of 2 (0%) DCC : 0 out of 6 (0%) SECONDARY: 0 out of 8 (0%) Edge Clocks: No edge clock selected. Regional Secondary Clocks: No regional secondary clock selected. ————— End of Clock Report —————
9、Why do I have a netsanitycheck error when I make a dynamic clock selector drive DDR (Double Data Rate) primitive components in my LatticeECP3 design?
LatticeECP3 device requires dedicated or primary clock resources to drive DDR (Double Data Rate) primitive components. The clock nets from the clock input pads to the destination DDR component must use pure primary or dedicated clock nets. If you implement a dynamic clock selector element in your RTL design, it may use general routing resources. This causes a design rule check violation and generates the netsanitycheck error.LatticeECP3 incorporates dedicated DCS (Dynamic Clock Select) function blocks that allows you to use only the primary clock resources. Although your RTL coding is an equivalent function of the DCS block, the synthesis tool may not use the DCS resource unless you explicitly instantiate the DCS block. The following Verilog example shows how to instantiate a DCS function in a LatticeECP3 design:Assume that “ck_a” and “ck_b” are two clock inputs, and “sel” is a clock selector input. It can be expressed as shown below, and note that it may not use the DCS block function.[Verilog] assign clk_out = (sel)? ck_a : ck_b;[VHDL] if (sel = ‘1’) then clk_out = ck_a; else clk_out = ck_b; endifTo use the dedicated DCS block function instead, instantiate the DCS primitive as shown below:[Verilog] DCS u1_dcs (.CLK0 (ck_a), .CLK1 (ck_b), .SEL (sel), .DCSOUT (clk_out));[VHDL] u1_dcs : DCS port map (CLK0 => ck_a, CLK1 => ck_b, SEL => sel, DCSOUT => clk_out);The use of DCS block will let you use fully dedicated primary clock resources, and you will not see the netsanitycheck error.